/*
 * =====================================================================================
 * Copyright (C) 2023 Ingenic Semiconductor Co.,Ltd
 * All Rights Reserved
 *
 * Filename     : reg_gpio.h
 * Author       : Keven <keven.ywhan@ingenic.com>
 * Created      : 2024/06/05 11:15
 * Description  :
 *
 * =====================================================================================
 */

#ifndef __REG_GPIO_H__
#define __REG_GPIO_H__

#include "reg_base.h"


/*************************************************************************
 * GPIO (General-Purpose I/O Ports)
 *************************************************************************/
#define MAX_GPIO_NUM	192

//n = 0,1,2,7
#define GPIO_PXPIN(n)		(GPIO_BASE + (0x00 + (n)*0x1000)) /* PIN Level Register */
#define GPIO_PXINT(n)		(GPIO_BASE + (0x10 + (n)*0x1000)) /* PORT Interrupt Register */
#define GPIO_PXINTS(n)		(GPIO_BASE + (0x14 + (n)*0x1000)) /* PORT Interrupt Set Register */
#define GPIO_PXINTC(n)		(GPIO_BASE + (0x18 + (n)*0x1000)) /* PORT Interrupt Clear Register */
#define GPIO_PXMSK(n)		(GPIO_BASE + (0x20 + (n)*0x1000)) /* PORT Interrupt Mask Register */
#define GPIO_PXMSKS(n)		(GPIO_BASE + (0x24 + (n)*0x1000)) /* PORT Interrupt Mask Set Reg */
#define GPIO_PXMSKC(n)		(GPIO_BASE + (0x28 + (n)*0x1000)) /* PORT Interrupt Mask Clear Reg */
#define GPIO_PXPAT1(n)		(GPIO_BASE + (0x30 + (n)*0x1000)) /* PORT Pattern 1 Register */
#define GPIO_PXPAT1S(n)		(GPIO_BASE + (0x34 + (n)*0x1000)) /* PORT Pattern 1 Set Reg. */
#define GPIO_PXPAT1C(n)		(GPIO_BASE + (0x38 + (n)*0x1000)) /* PORT Pattern 1 Clear Reg. */
#define GPIO_PXPAT0(n)		(GPIO_BASE + (0x40 + (n)*0x1000)) /* PORT Pattern 0 Register */
#define GPIO_PXPAT0S(n)		(GPIO_BASE + (0x44 + (n)*0x1000)) /* PORT Pattern 0 Set Register */
#define GPIO_PXPAT0C(n)		(GPIO_BASE + (0x48 + (n)*0x1000)) /* PORT Pattern 0 Clear Register */
#define GPIO_PXFLG(n)		(GPIO_BASE + (0x50 + (n)*0x1000)) /* PORT Flag Register */
#define GPIO_PXFLGC(n)		(GPIO_BASE + (0x58 + (n)*0x1000)) /* PORT Flag clear Register */
#define GPIO_PXGFCFG0(n)	(GPIO_BASE + (0x70 + (n)*0x1000)) /* PORT Glitch Filter Configure 0 */
#define GPIO_PXGFCFG0S(n)	(GPIO_BASE + (0x74 + (n)*0x1000)) /* PORT Glitch Filter Configure 0 Set */
#define GPIO_PXGFCFG0C(n)	(GPIO_BASE + (0x78 + (n)*0x1000)) /* PORT Glitch Filter Configure 0 Clear */
#define GPIO_PXGFCFG1(n)	(GPIO_BASE + (0x80 + (n)*0x1000)) /* PORT Glitch Filter Configure 1 */
#define GPIO_PXGFCFG1S(n)	(GPIO_BASE + (0x84 + (n)*0x1000)) /* PORT Glitch Filter Configure 1 Set */
#define GPIO_PXGFCFG1C(n)	(GPIO_BASE + (0x88 + (n)*0x1000)) /* PORT Glitch Filter Configure 1 Clear */
#define GPIO_PXGFCFG2(n)	(GPIO_BASE + (0x90 + (n)*0x1000)) /* PORT Glitch Filter Configure 2 */
#define GPIO_PXGFCFG2S(n)	(GPIO_BASE + (0x94 + (n)*0x1000)) /* PORT Glitch Filter Configure 2 Set */
#define GPIO_PXGFCFG2C(n)	(GPIO_BASE + (0x98 + (n)*0x1000)) /* PORT Glitch Filter Configure 2 Clear */
#define GPIO_PXGFCFG3(n)	(GPIO_BASE + (0xa0 + (n)*0x1000)) /* PORT Glitch Filter Configure 3 */
#define GPIO_PXGFCFG3S(n)	(GPIO_BASE + (0xa4 + (n)*0x1000)) /* PORT Glitch Filter Configure 3 Set */
#define GPIO_PXGFCFG3C(n)	(GPIO_BASE + (0xa8 + (n)*0x1000)) /* PORT Glitch Filter Configure 3 Clear */
#define GPIO_PXVDDIO(n)		(GPIO_BASE + (0x100 + (n)*0x1000)) /* PORT VDDIO-SEL Register */
#define GPIO_PXVDDIOS(n)	(GPIO_BASE + (0x104 + (n)*0x1000)) /* PORT VDDIO-SEL Set Register */
#define GPIO_PXVDDIOC(n)	(GPIO_BASE + (0x108 + (n)*0x1000)) /* PORT VDDIO-SEL Clear Register */
#define GPIO_PXPEL(n)		(GPIO_BASE + (0x110 + (n)*0x1000)) /* PORT Driver Disabled State Register0 */
#define GPIO_PXPELS(n)		(GPIO_BASE + (0x114 + (n)*0x1000)) /* PORT Driver Disabled State Set Register0 */
#define GPIO_PXPELC(n)		(GPIO_BASE + (0x118 + (n)*0x1000)) /* PORT Driver Disabled State Clear Register0 */
#define GPIO_PXPEH(n)		(GPIO_BASE + (0x120 + (n)*0x1000)) /* PORT Driver Disabled State Register1 */
#define GPIO_PXPEHS(n)		(GPIO_BASE + (0x124 + (n)*0x1000)) /* PORT Driver Disabled State Set Register1 */
#define GPIO_PXPEHC(n)		(GPIO_BASE + (0x128 + (n)*0x1000)) /* PORT Driver Disabled State Clear Register1 */
#define GPIO_PXDSL(n)		(GPIO_BASE + (0x130 + (n)*0x1000)) /* PORT Drive Strength Register0 */
#define GPIO_PXDSLS(n)		(GPIO_BASE + (0x134 + (n)*0x1000)) /* PORT Drive Strength Set Register0 */
#define GPIO_PXDSLC(n)		(GPIO_BASE + (0x138 + (n)*0x1000)) /* PORT Drive Strength Clear Register0 */
#define GPIO_PXDSH(n)		(GPIO_BASE + (0x140 + (n)*0x1000)) /* PORT Drive Strength Register1 */
#define GPIO_PXDSHS(n)		(GPIO_BASE + (0x144 + (n)*0x1000)) /* PORT Drive Strength Set Register1 */
#define GPIO_PXDSHC(n)		(GPIO_BASE + (0x148 + (n)*0x1000)) /* PORT Drive Strength Clear Register1 */
#define GPIO_PXSR(n)		(GPIO_BASE + (0x150 + (n)*0x1000)) /* PORT Slew Rate Register */
#define GPIO_PXSRS(n)		(GPIO_BASE + (0x154 + (n)*0x1000)) /* PORT Slew Rate Set Register */
#define GPIO_PXSRC(n)		(GPIO_BASE + (0x158 + (n)*0x1000)) /* PORT Slew Rate Clear Register */
#define GPIO_PXSMT(n)		(GPIO_BASE + (0x160 + (n)*0x1000)) /* PORT Schmitt Trigger Register */
#define GPIO_PXSMTS(n)		(GPIO_BASE + (0x164 + (n)*0x1000)) /* PORT Schmitt Trigger Set Register */
#define GPIO_PXSMTC(n)		(GPIO_BASE + (0x168 + (n)*0x1000)) /* PORT Schmitt Trigger Clear Register */
#define GPIO_PXIE(n)		(GPIO_BASE + (0x180 + (n)*0x1000)) /* PORT Receiver enable state Register */
#define GPIO_PXIES(n)		(GPIO_BASE + (0x184 + (n)*0x1000)) /* PORT Receiver enable state Set Register */
#define GPIO_PXIEC(n)		(GPIO_BASE + (0x188 + (n)*0x1000)) /* PORT Receiver enable state Clear Register */

#endif /* __REG_GPIO_H__ */

